This invention relates generally to frequency detectors and more particularly to frequency detectors adapted for use in clock recovery circuits which operate at relatively high data rates.
As is known in the art, frequency detectors have a wide range of applications. One application is in a clock recovery circuit. In such circuit, a stream of binary data is fed to the circuit. The clock recovery circuit if effect detects the frequency of the stream of binary data and produces clock pulses synchronized with the stream of binary data. That is, the clock recovery circuit recovers the clock pulses used to generate the stream of binary data.
One such clock recover circuit is described in an article entitled xe2x80x9cA 143-360 Mb/s Auto-Rate Selecting Data-Retimer Chip for Serial-Digital Video Signalsxe2x80x9d by David Poston and Alan Buchholz, published in 1996 IEEE International Solid-State Circuits Conference Paper FP 123.2 pages 196 and 197. The circuit described in this article includes a feedback loop made up of a frequency detector and a voltage controlled oscillator (VCO). The frequency detector is fed by the stream of binary data and the output of the frequency detector and drives the VCO to produce a train of clock pulses having the same frequency of the stream of binary data. The frequency detector then tracks changes in the frequency of the stream of binary data so that the frequency of the clock pulses produced by the VCO the same as the frequency of the stream of binary data (i.e., the clock pulses which produced the binary data is thereby recovered). A phase lock loop (PLL) is also provided. The PLL includes a phase detector which is also fed by the stream of binary data and the clock pulses produced by the VCO. Once the frequency of the stream of binary data is being tracked by the VCO (i.e., the clock pulse frequency is the same as the frequency of the stream of binary data), the PLL adjusts the VCO such that the center of the each binary data is aligned with the rising (or falling) edge of a VCO produced clock pulse. Thus, the stream of binary data is properly time-aligned with the VCO produced clock pulses so that such binary data may be sampled in response to the rising edge (or falling edge) of the VCO clock pulse for further, down-stream processing.
The frequency detector used in the above referenced article operates on the concept of rotational frequency detection. That is, the frequency detector produces an output signal related to the difference between the frequency of the stream of binary data and the frequency of the VCO clock pulses. In general, if there is a frequency error between two signals, their phase relationship will change with time; the rate of change of phase is proportional to the frequency error. The circular diagrams of FIG. 1 are phasor representations of the VCO clock pulses. A ray from the origin rotates counter-clockwise with time at an angular rate xcfx89VCO. The frequency detector operates by taking snapshots or samples of this VCO phasor at the instants of occurrence of data transitions; (i.e., the rising and falling edges of the stream of binary data) the frequency error information is contained in the rate and direction of rotation of these phasor samples over time.
Imagine for analogy a bicycle wheel with a red ribbon tied around one of its pokes, spinning at a constant rate in a dark room. If a strobe light is triggered by an electrical signal at the same frequency as the wheel""s rotational rate, the ribbon will appear to be fixed in angular position. If the frequency of the strobe is varied slightly, the ribbon will begin rotating in a direction determined by the polarity of the frequency error, at a rate xcfx89e proportional to the magnitude of the error (the number of complete revolutions per second of the ribbon is exactly equal to frequency difference in Hz). In this way edges in the data xe2x80x9cstrobexe2x80x9d the VCO phasor. Note that each VCO produced clock pulse period is divided into four phases or quadrants, labelled A, B, C, and D in FIG. 1. The frequency detector operates by xe2x80x9cwatchingxe2x80x9d the xcfx89e phasor as it rotates past the B-C border (i.e., boundary BBC) in the phasor diagram. For example, if a data transition is detected in B, then C, the detector outputs a xe2x80x9cpump-downxe2x80x9d pulse, reflecting the fact the data rate is lower than the VCO frequency; conversely, if a transition is detected in C, then B, the frequency of the data is higher than that of the clock pulses, and a xe2x80x9cpump-upxe2x80x9d pulse is generated. This method is feasible so long as the frequency difference is such that the change is angular position of the ribbon is less than half a revolution on consecutive strobe flashes (|xcfx89e| less than 50% of xcfx89data).
The process of frequency detection is complicated by the fact that the data at the input is random; a data transition may or may not occur in a given data period. Returning to the bicycle wheel analogy, the strobe is intermittent, flashing (on average) half the time. One might image that, for small enough frequency differences, it would still be possible to determine the apparent angular velocity xcfx89e (magnitude and direction) of the strobe ribbon. It is may be shown that the range of the frequency detector is in excess of xc2x125% of xcfx89data with random data.
After phase acquisition, a phase lock loop (PLL) maintains coincidence between the. data transitions and the rising edge of the clock pulse (the A-D boundary, BAD in the phasor diagram). The frequency detector senses rotation at the boundary between the quadrants B and C, (i.e., boundary BBC) so that it is inactive after phase-lock is achieved. Jitter on either side the clock pulses or the data can conceivably trigger the frequency detector, this would require a jitter event of greater than 90 degrees (causing a data transition to occur in quadrant B or C), followed by a jitter even of greater than 180 degrees (or  greater than 90 degrees in the opposite direction). In the even of such an occurrence, the resulting error pulse must not have enough gain to throw the PLL out of lock.
The specific frequency detector described in the above referenced article includes a series of xe2x80x9cDxe2x80x9d flip-flops having their xe2x80x9cDxe2x80x9d input fed by the VCO clock pulses (xe2x80x9cin-phasexe2x80x9d and xe2x80x9cquadraturexe2x80x9d clock pulses) and enabled by detected edges of the stream of binary data. The outputs of the flip-flops are fed to a combinational logic (i.e., UP/DN Decoder). The combinational logic produced a pair of control signals each time the B-C boundary, BBC, is crossed; one control signal to cause a charge pump to xe2x80x9cpump-upxe2x80x9d and increase the VCO clock frequency and control signal to cause the charge pump to xe2x80x9cpump-downxe2x80x9d and decrease the VCO clock frequency. The pair of control signals is fed to an OR gate of a decoder lock-out circuit. Thus, the OR gate produces a control signal each time B-C boundary, BBC, is crossed. The lock-out circuit includes a latch fed by the output of the OR gate and one of the flip-flops. Such one of the flip-flops indicates when the data vector is in the left hand plane (i.e., quadrants B or C). The decoder lock-out circuit prevents multiple xe2x80x9cpump-upxe2x80x9d/xe2x80x9cpump-downxe2x80x9d pulses from being produced as a result of jittering across the B-C boundary, BBC, during low slip rates (i.e., low frequency differences).
While such frequency detector circuit works for data rates in the range of 143-360 Mb/s, in some application clock recovery circuits are required to operate with data rates in the order of 600 MHz.
In accordance with the present invention, a frequency detection system is provided for producing clock pulses having a frequency equal to the frequency of a stream of binary data. The system includes a voltage controlled oscillator for producing the clock pulses. The frequency of such clock pulses changes in accordance with a control signal. Each period of the clock has four sequential, one-quarter period phases. Adjacent phases are separated by boundaries to divide each clock pulse period into four quadrants. A frequency detector is fed by detected edges of the stream of binary data and the clock pulses for producing the control signal in accordance with the difference in frequency between the frequency of the clock and the frequency of the stream of binary data. The frequency detector includes a pair of clock pulse/detected data edge latches fed by the clock pulses and the detected edges of the stream of binary data. One of such latches stores a binary signal indicating when a detected edge occurs during a first quadrant and another one of latches produces a binary signal indicating when a detected edge occurs during a second quadrant contiguous to the first quadrant of the clock. A network, fed by the clock pulse/detected data edge latches, the clock pulses produced by the voltage controlled oscillator, and a xe2x80x9cblockxe2x80x9d/xe2x80x9cunblockxe2x80x9d control signal, is adapted to produce the control signal when detected data edges crosses the boundary between the first and second quadrants and when the xe2x80x9cblockxe2x80x9d/xe2x80x9cunblockxe2x80x9d control signal is an xe2x80x9cunblockxe2x80x9d condition. A lock-out circuit produces the xe2x80x9cblockxe2x80x9d/xe2x80x9cunblockxe2x80x9d control signal to place the network in the xe2x80x9cblockxe2x80x9d condition subsequent production of the control signal and to maintain such xe2x80x9cblockxe2x80x9d condition until a subsequently detected data edge crosses a different one of the boundaries to thereby place the network in the xe2x80x9cunblockxe2x80x9d condition.